Many digital devices, such as those classified as System-On-Chip (SOC) devices, contain a bus structure where multiple masters and multiple slaves share a common internal bus. The internal bus can be defined as a standard interface between the masters and slaves, making the development and implementation of the masters and slaves relatively simple. The common internal bus also provides a flexible platform to which digital systems may be designed.
FIG. 1 illustrates a conventional bus structure 10 for an SOC device, in which a single internal bus 12 connects a plurality of masters 14 with a plurality of slaves 16. Also connected to the internal bus 12 is a bus arbiter 18, which monitors the internal bus 12 and grants ownership of the internal bus 12 to the masters 14 when needed. Once ownership of the bus is obtained, a master 14 is allowed to control a desired slave 16. Since the internal bus 12 provides a standard interface, any arbitrary number of masters 14 or slaves 16 can be connected to the internal bus 12.
Devices considered to be masters 14 include, for example, general purpose processors, digital signal processors (DSPs), universal bus interface (USB) host controller, DMA controller, LCD controller, etc. The slaves 16 may include devices such as memory controllers, serial peripheral interface (SPI) devices, real-time clocks, watchdog timers, pulse width modulators, interrupt controllers, UARTs, etc. As is well known in the art, any master 14 can seek ownership of the internal bus 12 by sending a request to the bus arbiter 18. When there are no conflicting requests, then the bus arbiter 18 normally grants ownership to the requesting master 14, and the master 14 gains ownership of the internal bus 12 and is allowed to access a particular slave 16. When multiple masters 14 request bus ownership at one time, then the bus arbiter 18 utilizes a predefined arbitration protocol to grant ownership to only one master at a time. The arbitration protocol is followed in order to guarantee that each master is serviced in a manner to maximize the performance and stability of the system as a whole.
The conventional bus structure 10 of FIG. 1 allows great flexibility in control, such that any master 14 can access or control any slave 16. In the case where there are five master and twenty slaves, there would be one hundred master/slave combinations possible. One disadvantage of this bus structure 10, however, is that while one master is accessing one slave, a second master cannot be simultaneously accessing a second slave. In this regard, only one master 14 and only one slave 16 can be active at any time. If two masters 14 attempt to gain ownership of the internal bus 12, then one master 14 must wait for the first one to complete the transaction before the second one can begin. Since the internal bus 12 is only capable of handling one master/slave connection at a time, the conventional bus structure 10 is therefore limited by the bandwidth of the internal bus 12. A disadvantage of this conventional bus structure 10 is that a bottleneck situation can result when multiple simultaneously requests are made.
A couple solutions have been proposed to overcome the deficiencies of the conventional system. One solution has been to increase the operating frequency of the internal bus. However, this complicates the design of the master/slave interfaces and typically would require redesigning the masters and slaves in order that they will be able to operate at the higher speed. Another solution has been to widen the associated data bus portion of the internal bus to increase the data bandwidth, allowing more information to be transferred during each cycle. However, this approach increases the amount of logic necessary to implement each master/slave interface on the internal bus. For those masters and/or slaves already in existence or those in the process of being designed, increasing the internal bus frequency or data width might require additional work to redesign the components.
A new internal bus structure, which eliminates the undesirable bottlenecks resulting from the conventional system, is desired. Such a new system should allow more than a single master/slave transaction to occur at a time while still maintaining the same amount of flexibility present in the prior art. It would further be beneficial for such a new system to operate with a frequency or a data bandwidth that does not necessarily have to be increased in order to achieve these objectives. The present disclosure provides a system to alleviate the bus bandwidth limitation of the prior art without increasing the operating frequency or data width of the internal bus interfaces.